1. Field of the Invention
The present invention relates to data communications circuits and, in particular, to an asynchronous receiver/transmitter (UART), which is operable in alternate modes for use with a variety of CPU's and peripherals, and other applications where first-in, first-out memories are used.
2. State of the Art
Commercially available UARTs include a receiver FIFO memory and a transmitter FIFO memory with each of these FIFO memories, in actuality, comprising two or more FIFO memories each of a selected fixed length and depth to maximize the compatibility of the UART with other devices in different environments.
Similarly, multi-decisional interrupt circuits are included with a FIFO memory to insure the timely reading of the data stored in the FIFO. Each of the decision steps are implemented with a separate interrupt circuit.
U.S. Pat. No. 4,823,312 issued to Michael, et al. discloses a UART that has both of those functions, and more specifically each of the receiver FIFO memory and the transmitter FIFO memory includes a FIFO memory that performs the function of a buffer to store multiple bits of data. The number of bytes stored is selected as a trigger level at which a first of the decisional circuits generates an interrupt to the CPU to indicate that there is data available in the FIFO. With a large block of data, reading and writing continues until eventually the end of the block of data is reached. This results in there being data in the FIFO that is possibly below the selected trigger level. If that happens, there is no way for the CPU to know that there is still data in the FIFO without a second decisional interrupt circuit. Without the second decisional interrupt circuit that data would be lost.
The second decisional interrupt circuit that is incorporated into the prior art is a timing circuit that monitors the length of time since the FIFO has been accessed to either read from it or to write to it. If that time exceeds a selected period, a time-out interrupt is generated to the CPU to read the remaining data in the FIFO.
It would be desirable to have a UART that incorporates a variable length and depth FIFO to provide the maximum variability of the FIFO size to better match it to various applications without increasing the chip size for the overall device. Additionally, it would be desirable to minimize the size of the, and to have one, multi-decisional interrupt circuit to maintain control of the growth of the size of the semiconductor chip that the overall device requires. The improvements of the present invention provide both goals.